1. Field of the Invention
The present invention relates to a semiconductor memory device suitable for a multi-value flash memory of which charge storage layers are spatially separated, and a manufacturing method thereof.
2. Description of the Related Art
Conventionally, there has been such a limitation in a multi-value flash memory that electron injection during write operation in a memory cell of MONOS (Metal/Oxide/Nitride/Oxide/Semiconductor) structure is possible only in the regions at both ends of a gate; thereby electrons which are injected into traps of a nitrided film are accumulated. These accumulated electrons cause a shift in a threshold voltage of a cell transistor. As a result, an electric current value of the cell transistor during read operation may vary to “1” or “0(zero)” in terms of information.
Generally, in such an element structure, such electrons as injected and held in a source side of the cell transistor largely affect the shift of the threshold voltage of the cell transistor. Therefore, it is possible to obtain two bits of information, which is represented as four values: “00”, “01”, “10”, and “11”, in one memory cell by conducting read operation of the state of accumulated electrons of both ends of the gate twice at the source and at a drain by turns.
In a memory cell of conventional structure, there is placed a charge storing film, commonly a silicon nitride film, over the whole area of the gate, thereby charge redistribution may occur. The charge redistribution may vary the shifting amount of the threshold voltage and concurrently rewrite information of the other side of the gate, resulting in further readout error.
Accordingly, such an approach has been developed in order to prevent the charge redistribution that a charge storage layer is electrically divided into portions, and charge storing layers formed at both ends of the gate and a control gate are so formed as in a self-aligned manner. In this approach, charge is to be stored at both ends of the gate of the charge storage layers, so that charge redistribution is prevented by forming a separation oxide film.
In the prior art, when such a separation oxide film is formed, first, an oxide film as a material film of the separation oxide film, an oxide film for an ONO film, and a polysilicon film (polycrystalline silicon film) for a gate electrode are formed sequentially on a tunnel oxide film. After that, the polysilicon film and the two oxide films are processed to take shape of a gate by anisotropic etching such as RIE (reactive ion etching) or the like. In the course of the process, overetching is conducted to the oxide films thereby an outer edge portion of the oxide film, which is used as the material film of the separation oxide film, is made retreat, so that the separation oxide film is formed.
A prior art is disclosed in Japanese Patent Laid-open No. 2001-168219.